This invention relates to a matrix logic circuit network which occupies a small area, and is suitable for large-scale integration.
With recent advances in integrated-circuit manufacturing techniques, a large-scale logic circuit network can be realized in one chip. However, the large-scale version of the logic circuit network makes it difficult to design and requires a long time for its development. In particular, custom-made LSIs, which require the specific design of IC patterns for every application, encounter technical difficulties in the automatic design with the aid of a computer, because a variety of circuit network patterns are required. For this reason, the design of such LSI's must resort largely to manpower and the development of the custom-made LSI's is most time consuming. To cope with this difficulty, semicustom-made LSI developing techniques such as a building block method, gate array method and the like have been proposed which enable, by limiting the variations of circuit network patterns, the automatic design of circuit network patterns and reduces LSI developing processes.
These methods, however, have a disadvantage that a computer must be used for a long time, since an algorithm for automatic layout and wiring is complicated and the amount of calculations is extremely large.
For solving this problem, another method has been proposed, called a programmable logic array (PLA), in which further limits he layout and wiring of the circuit patterns. With this method, a desired logic circuit is formed by cascading an AND-circuit matrix and an OR-circuit matrix. In the OR matrix, however, the number of transistors which are actually used is very small. This tendency becomes more distinctive as the matrix becomes larger, resulting in poor integration density. In this respect, it was difficult to realize a large system by the PLA.
It is a common practice to perform a software simulation using a computer or a hardware simulation using a breadboard, for checking the function of a designed system.
With all of these conventional methods, however, the computer must be used for a long period of time for the purpose of software simulation and an operation test linked with other devices cannot be performed. For the hardware simulation, the manufacturing and adjustment of the breadboard requires much of time, labor and cost.